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Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
HIGHEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
RISES ABOVE THIS LEVEL
BUILT-IN 8 TO 64 LSBs
OF HYSTERESIS
RANGE OF VALUES THAT DO NOT CAUSE AN ALARM
BUILT-IN 8 TO 64 LSBs
OF HYSTERESIS
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
FALLS BELOW THIS LEVEL
*ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE.
WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ
FOR ALARM TO BE DEASSERTED.
Figure 7. Window-Threshold-Mode Diagram
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE FALLS
BELOW THIS LEVEL*
HIGH THRESHOLD
LOW THRESHOLD
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE RISES
ABOVE THIS LEVEL*
LOWEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
Flag register. Configure ALARM for open-drain/push-
pull and active-high/active-low by setting the respective
bits in the Hardware Alarm Configuration register.
SAFE1/SAFE2 Outputs
Set up the SAFE1 and SAFE2 outputs to allow Wired-
OR/AND-type logic functions or to create additional
interrupt-type signals to replace or supplement the
existing ALARM output. SAFE1 and SAFE2 do not have
any internal pullup/pulldown devices.
The SAFE1 and SAFE2 output buffers are CMOS-com-
patible, noninverting, output buffers capable of driving
to within 0.5V of either digital rail. The SAFE1 and
SAFE2 outputs power up as active-high CMOS outputs
with standard logic levels. Configure the SAFE1 and
SAFE2 outputs for open-drain or push-pull by setting
the appropriate bits in the Hardware Alarm
Configuration register. When configuring SAFE1 and
SAFE2 as open-drain outputs, an external pullup resis-
tor is required.
BUSY Output
The BUSY output is forced high to show that the
MAX1385/MAX1386 are busy for a variety of reasons:
? The ADC is in the middle of a user-commanded con-
version cycle (but not in continuous convert mode)
? The ADC is in the middle of an internally triggered
conversion cycle (for a self-calibration measurement)
? The device is in the middle of DAC calibra-
tion calculations
? The device is in the middle of power-up initialization
? One of the PGA channels is undergoing self-calibration
The serial interface remains active regardless of the
state of the BUSY output. Wait until BUSY goes low to
read the current conversion data from the FIFO. When
BUSY is high as a result of an ADC conversion, do not
enter a second conversion command until BUSY has
gone low to indicate the previous conversion is com-
plete. The rising edge of BUSY occurs on the next inter-
nal oscillator clock after the start of a new conversion
(either by CNVST or an interface command).
24
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